Project Digital

NOTE:

Project Description:

In this project, you will design a simple Arithmetic Logic Unit $($ALU$)$ using Verilog

Hardware Description Language $($HDL$).$ The ALU should be capable of performing four

basic arithmetic and logic operations: addition, subtraction, bitwise AND, and bitwise

OR$.$

Objective:

To develop a comprehensive understanding of Verilog HDL for hardware

description.

To design and implement a simple ALU with four basic functionalities.

To explore structural, dataflow, and behavioral modeling techniques in Verilog.

Tasks:

ALU Design:

Define inputs and outputs of the ALU

Select four essential arithmetic and logical operations to implement $($e$.$g$.,$

addition, subtraction, AND, OR$)$

Create a block diagram representing the ALU's structure.

Verilog Modules:

Develop a top$-$level ALU module with appropriate input$/$output ports.

Design separate modules for each of the four chosen operations, utilizing

a combination of structural and behavioral modeling approaches.

Modules: Adder, Subtractor, AndGate, OrGate, and ALU

$($toplexel module$).$

The ALU design should be modular, comprising separate modules

for each functionality.

Implement the modules using structure, dataflow, and behavioral

modeling as below:

Utilize structural modeling for Adder, Subtractor, and logic

gates.

Implement dataflow modeling for connecting the modules.

Utilize behavioral modeling for the top$-$level ALU module.

Input$/$Output

The ALU should take two $4-$bit inputs $($A and B$).$

Include a $3-$bit control input $(Q$ pCede$)$ to select the operation:

$3\text{'}$b$000$: Addition

$3\text{'}$b$001$: Subtraction

$3\text{'}$b$010$: Bitwise AND

$3\text{'}$b$011$: Bitwise OR $$ Output the result $($Result$)$ of the

selected operation.

Testing and Simulation

Test various combinations of input values and control codes to ensure the

ALU operates as expected. Apply a variety of input test cases to cover all

possible combinations.

Simulate the ALU Components$/$Modules using a Verilog simulator and

analyze the results

Simulate the ALU using a Verilog simulator and analyze the results.

Documentation:

Provide clear and concise comments within the Verilog code for better

understanding.

Prepare a well$-$formatted project report detailing the design process, code

implementation, simulation results, and conclusions.

Evaluation:

Correctness of the ALU's functionality

Efficiency of the Verilog code.

Quality of the simulation results.

Clarity of documentation and project report. Additional Guidelines:

Adhere to Verilog coding conventions and best practices. $-$ Consider using a

design hierarchy for better organization.

Thoroughly test the ALU under various input scenarios.

Document any assumptions or design choices made during the project.

Submission Requirements:

You need to submit the following files as one compressed folder $($e$.$g$.,.$zip, $.$rar$)$ for your

project by January, $23$rd$,2024($up to midnight$).$ Then, name your folder as

$($hdIProject$\_$LastName$\_$FirstName$\_$StudetnsID.zip$).$

Verilog HDL source code for each module. Verilog code for the ALU and its

modules.

Simulation files. The simulation results $($waveforms$)$ of every individual

component.

The schematic files for the whole system $($that shows the structural modeling of

the final system design$)$

Comprehensive project report $($in PDF format$),$ including design details,

simulation results, and conclusions.

The project discussion will be based on the above bullets, as well as$,$ you will be

asked to slightly modify the system. This way, we can assess your understanding

of the project.

Best of luck with your ALU design!