Hi! I have this Verilog 2001 code and i whould like to create a testbench file for it in order to run it into modelsim.

module sum_of_difference (input wire [4:0] A, B, C, D, E,

output wire sum_of_difference);

assign sum_of_difference = A + B + C + D + E;

endmodule

If someone could help me i would be gratefull!