Hi I$\text{'}$m trying to undersand the classical method of control unit design through the book I$\text{'}$m using, but I can't make anything out of them such as its connection to the gcd processor presented on the figures please help!

I'll definitely upvote when you're able to help me understand it$.$ Thanks!Classical method. The major steps of the classical design method are as fol$-$

lows:

Construct a $P-$row state table that defines the desired input$-$output behavior.

Select the minimum number $p$ of D$-$type flip$-$flops and assign a $p-$bit binary

code to each state.

Design a combinational circuit $C$ that generates the primary output signals $\{z_i\}$

and the secondary outputs $\{D_i\}$ that must be applied to the flip$-$flops.

We now apply this method to the design of the control unit CU for the $gcd$ pro$-$

cessor. We have already constructed the necessary state table $($Figure $5\mathrm{.}7).$ Since

there are four states, we require two flip$-$flops, whose outputs $D_1{D}_0=y_1{y}_0$ define

CU's internal states. We assign the binary patterns to the four states in the follow$-$

ing obvious way:

$S_0=00$

$S_1=01$

$S_2=10$

$S_3=11$

We note in passing that the state assignment pattern affects the complexity of the

circuit in subtle ways.

At this point we can construct a binary version of the state table, the excitation

table, as shown in Figure $5\mathrm{.}8.$ The D flip$-$flop's characteristic equation $D_i^{+}(t+1)=$

$D_i(t)$ defines the inputs $D_1^{+}$and $D_0^{+}$to the flip$-$flops. CU's combinational logic $C$

can now be derived from the excitation table using any available manual or auto$-$

matic method. Suppose, for instance, that we use two$-$level sum$-$of$-$products $($SOP$)$

minimization. It is easily checked that $C$ is defined by the following SOP equa$-$

tions, which lead directly to the design of Figure $5\mathrm{.}9.$ Note that all gates in an

AND$-$OR SOP circuit can be changed to NANDs to produce a NAND$-$NAND real$-$

ization of the original function.

$D_1^{+}=(\frac{?}{\text{b}\text{a}\text{r}}(xR>0))+(xRYR)+D_0$

$D_0^{+}=D_1*D_0+(\frac{?}{\text{b}\text{a}\text{r}}(xRxR))\frac{*}{b}ar(D{)}_0+(\frac{?}{\text{b}\text{a}\text{r}}(xR>0))\frac{*}{b}ar(D{)}_0$

Subtract $=D_1\frac{*}{b}ar(D{)}_0$

Swap$\frac{}{b}=ar(D{)}_1*D_0$

Select $xY\frac{?}{b}=ar(D{)}_1\frac{*}{b}ar(D{)}_0$

Load $xR\frac{?}{b}=ar(D{)}_0\frac{+}{b}ar(D{)}_1$

Load $YR\frac{?}{b}=ar(D{)}_1$

Figure $5\mathrm{.}8$

Excitation table for the control unit of the $gcd$ processor.

$D_1^{+}=(\frac{?}{\text{b}\text{a}\text{r}}(xR>0))+(xRYR)+D_0$

$D_0^{+}=D_1*D_0+(\frac{?}{\text{b}\text{a}\text{r}}(xRxR))\frac{*}{b}ar(D{)}_0+(\frac{?}{\text{b}\text{a}\text{r}}(xR>0))\frac{*}{b}ar(D{)}_0$

Subtract $=D_1\frac{*}{b}ar(D{)}_0$

Swap$\frac{}{b}=ar(D{)}_1*D_0$

Select $xY\frac{?}{b}=ar(D{)}_1\frac{*}{b}ar(D{)}_0$

Load $xR\frac{?}{b}=ar(D{)}_0\frac{+}{b}ar(D{)}_1$

Load $YR\frac{?}{b}=ar(D{)}_1$