Hints: For $5\mathrm{.}5,$ part b$,$ in order for step $3$ to be the bottleneck, you need to find a positive batch size such that under this batch size, step $3\text{'}$s capacity is no larger than Step $1\text{'}$s capacity, and step $3\text{'}$s capacity is also no larger than step $2\text{'}$ capacity. If such a batch size does not exist, then it is not possible for step $3$ to be the bottleneck.Q$5\mathrm{.}5($JCL Inc.$)$ JCL Inc. is a major chip manufacturing firm that sells its products to computer manufacturers like Dell, HP$,$ and others. In simplified terms, chip making at JCL Inc. involves three basic operations: depositing, patterning, and etching.

Depositing: Using chemical vapor deposition $($CVD$)$ technology, an insulating material is deposited on the wafer surface, forming a thin layer of solid material on the chip.

Patterning: Photolithography projects a microscopic circuit pattern on the wafer surface, which has a light$-$sensitive chemical like the emulsion on photographic film. It is repeated many times as each layer of the chip is built.

Etching: Etching removes selected material from the chip surface to create the device structures.

The following table lists the required processing times and setup times at each of the steps. Assume that the unit of production is a wafer, from which individual chips are cut at a later stage.

Note: A setup can only begin once the batch has arrived at the machine.

$\backslash$table$[[$Process Step $i^{-1},1$ Depositing,$2$ Patterning,$3$ Etching$],[$Setup time,$45$min.,$30$min.,$20$min.$],[$Processing time,$0\mathrm{.}15$min$\frac{.}{u}$nit,$0\mathrm{.}25$min$\frac{.}{u}$nit,$0\mathrm{.}20mi\frac{n}{u}$nit