Homework $3$ Part $2$ Instructions

$***$ Need K$-$maps drawn out when needed, Need Truth Tables drawn out when needed. Need Digital Works implementation disaplayed for each

In this part, you are asked to design a $4-$bit ALU in Digital Works. You may break down the design into the following steps$/$blocks$.$ Make sure to thoroughly test every block before moving to the next step. Testing and thorough understanding of each individual macro will be evaluated during check off with the instructor. Here are more details about each block:

$1.$ Design a full adder block$/$macro$,$ addl. addl has three inputs $(\backslash ($ a$,$ b $\backslash ),$ and CarryIn$)$ and two outputs $($Sum and CarryOut$)$ as shown in the figure below. Each input$/$output is $1-$bit.

The adder truth table is shown below:

The logic equations are thus:

CarryOut $\backslash (=(\backslash$mathrm$\{$a$\}\backslash$cdot $\backslash )$ CarryIn $\backslash ()+(\backslash$mathrm$\{$b$\}\backslash$cdot $\backslash )$ CarryIn $\backslash ()+(\backslash$mathrm$\{$a$\}\backslash$cdot $\backslash$mathrm$\{$b$\})\backslash )$

Sum $\backslash (=\backslash$mathrm$\{$a$\}\backslash )$ xor b xor CarryIn

And the corresponding logic circuit will look like the one in the figure below:

For a refresher on how to extract the logic equation and circuits, check appendix $7$ in the

zybooks textbook.

Don't forget to thoroughly test the individual macro before moving to the next step.

Design a multiplexer macro, mux$2\_1.$ mux$2\_1$ has two data inputs $($in $1$ and in$2)$ and one

data output $($out$).$ Each input$/$output is $1-$bit. The multiplexer has one select line $($sel$)$ that

controls which input is passed to the output as shown below:

You will need to use truth table and k$-$map to come up with the logic equation for the

multiplexer block, and then map the logic equation to the respective logic circuit as

shown for the full adder above and as you did in CS $231.$

Don't forget to thoroughly test the individual macro before moving to the next step.

Design a multiplexer macro, mux$4\_1.$ mux$4\_1$ has four data inputs $($in $1,$ in $2,$ in $3,$ and

in$4)$ and one data output $($out$).$ Each input$/$output is $1-$bit. The multiplexer has a $2-$bit

selection line $($sell and sel$2)$ that controls which input is passed to the output. Hint: you

may use $3$ of the mux$2\_1$ macros from step $2$ to build this multiplexer as shown below:

Design $1-$bit ALU macro, alu$1,$ using the two multiplexer macros and the full adder

macro from the previous steps. The ALU has three data inputs $($ a$,$b$,$ and less$),$ four

control signals $($Binvert$,$ CarryIn, Operation$1,$ and Operation$2),$ and one data output

$($Result$)$ as shown in the following figure. The ALU supports logical and, logical or$,$ add,

subtract, and set if less than operations as explained in class.

Don't forget to thoroughly test the $1-$bit ALU before moving to the next step.

Note: you may need to create another macro alul$\_$extra that is a copy of alul but

has an additional output called Set which is the adder output. This will be used as

ALU$3$ in the next step to support the sit functionality.

Design a $4-$bit ALU using the alul macro from step $4($and alu$1\_$extra$).$ The $4-$bit ALU

has two data inputs $($a and b$)$ and one data output $($Result$),4-$bits each $($you may call

them a$0,$a$1,$a$2,$ and a $3$ and so on$...)$ The ALU also has four control signals $($Binvert$,$

CarryIn, Operation $1,$ and Operation$2)$ as explained in the lecture and depicted in the

picture below. Note that the ALU picture from the slides has $32$ alul but, in this

homework, you only need to have $3$ alul macros and $1$ alul$\_$extra macro. The less input

for ALUO is connected to Set output of ALU$3,$ which is the adder output for the most

significant alu $($ALU$3).$ The less data input is $0$ for the remaining alus $($ALU$3,$ ALU$2,$

and ALU$1).$ You may ignore the overflow detection output shown below.