Question: . Homework: Shift Register Operation CO initial clock rising In Out DQ edge causes In data entry to A FF DQ DO DO .C1 edge

Homework: Shift Register Operation CO initial clock rising In Out DQ edge causes In data entry to A FF DQ DO DO .C1 edge of the clock pulse enters the secondock CP In bit into A and shifts A-bit into B. Initially unknown states are denoted by CP In TO T1 T2 T3 T4 TS T6 C Out 0 0 0 0 .Draw the circuit and complete the last three rows of the table

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