How does adding the E state $($go from MSI to MESI$)$ impact the amount of traffic on

the shared bus? Why? State any assumptions you make.

B$)$ In the same system for the same cache block, why can$$t two caches be in states E

and S simultaneously?

C$)$ In a multicore system, you are are running the code on

the right on each core, and it suffers from false sharing. You

can assume t$\_$id is set to a unique thread identifier $($e$.$g$.$

$0-15).$ How could you change the code to reduce false

sharing?