How does the initial block work?

How come we didn't use an initial block in the FIR to force the registers to a valid state? $($Hint: what happens to a module with initial blocks during synthesis?$)$

Register In is driven on the negative edge of the clock. Why not the positive edge? Would this cause a violation? If so$,$ what type?

In the line generate the simulated clock, a special operator # is used. What is this operator?

Is the line generating the clock a continuous assign statement?