1. How does this data-path implement the INCA, ADDI, LDBI and LDA operations?
2. The data-path has a maximum reliable operating speed (Clk). What determines this speed? (i.e.,
   how would you estimate the data-path circuit clock)?
3. What is a reliable limit for your data-path clock?

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1. Objectives The objective of this lab is to build and test the data-path for a 32-bit processor. Students have designed and unit tested most of the components (PC, Registers, data memory and ALU) required for data-path in the previous labs. The block diagram of the data-path is illustrated in Figure 1. In this lab, students will interconnect these components together to create the CPU's data-path. Sufficient testing will also need to be done to ensure that the CPU data-path functions correctly. CPU specifications are described in another document, CPU Specification which is available on the lab webpage outline instruction specifications to help you assert the correct control signals for testing. Note that the Instruction Memory, M[INST] will be implemented in Lab6. UZE Upper Zero Extender LD_IR CLR_IR IR LZE LZE 32 A_Mux RED 0 LD_A CLR_A Reg_Mux 8 B_Mux LD_B CLR_B A RED Reducer Unit LD_PC, CLR_PC INC_PC LZE B 32 addr PC data_in MEM_IN UZE Data Memory M[ADDRS] LZE ADDR_OUT EN, WEN 1- 32 Figure 1: CPU Data-Path 32 32 32 LZE data_out IM MUX1 0 IM_MUX2 1 2 Lower Zero Extender M[INST] (lab 6) MEM_OUT 32 ALU OP ALU Zero 32 CarryOut DATA IN DATA_MUX 32 2 DATA BUS 1. Objectives The objective of this lab is to build and test the data-path for a 32-bit processor. Students have designed and unit tested most of the components (PC, Registers, data memory and ALU) required for data-path in the previous labs. The block diagram of the data-path is illustrated in Figure 1. In this lab, students will interconnect these components together to create the CPU's data-path. Sufficient testing will also need to be done to ensure that the CPU data-path functions correctly. CPU specifications are described in another document, CPU Specification which is available on the lab webpage outline instruction specifications to help you assert the correct control signals for testing. Note that the Instruction Memory, M[INST] will be implemented in Lab6. UZE Upper Zero Extender LD_IR CLR_IR IR LZE LZE 32 A_Mux RED 0 LD_A CLR_A Reg_Mux 8 B_Mux LD_B CLR_B A RED Reducer Unit LD_PC, CLR_PC INC_PC LZE B 32 addr PC data_in MEM_IN UZE Data Memory M[ADDRS] LZE ADDR_OUT EN, WEN 1- 32 Figure 1: CPU Data-Path 32 32 32 LZE data_out IM MUX1 0 IM_MUX2 1 2 Lower Zero Extender M[INST] (lab 6) MEM_OUT 32 ALU OP ALU Zero 32 CarryOut DATA IN DATA_MUX 32 2 DATA BUS