Pictured here is the master-slave register circuit presented in lecture: 13 QM T CLK How would...

 

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Pictured here is the master-slave register circuit presented in lecture: 13 QM T CLK How would you modify the circuit to add the following features: an asynchronous reset, a syn- chronous set and an enable signal? Note that when the enable signal is low, the output of the register should return its previous state regardless of any clock transitions. Show the modifications you would make for each feature. Try to minimize the total number of transistors. You may use any simple 2 input gates and NMOS or PMOS transistors, and you may replace the inverters in the flip flop circuit, as long as you maintain the desired functionality. Pictured here is the master-slave register circuit presented in lecture: 13 QM T CLK How would you modify the circuit to add the following features: an asynchronous reset, a syn- chronous set and an enable signal? Note that when the enable signal is low, the output of the register should return its previous state regardless of any clock transitions. Show the modifications you would make for each feature. Try to minimize the total number of transistors. You may use any simple 2 input gates and NMOS or PMOS transistors, and you may replace the inverters in the flip flop circuit, as long as you maintain the desired functionality.

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