Question: hw 7 elearning file Alu.sv module ALU ( Result , N , Z , C , V , A , B , ALUcontrol ) ;

hw 7 elearning file
Alu.sv
module ALU(Result, N,Z,C,V,A,B, ALUcontrol);
input [7:0] A,B;
input [1:0] ALUcontrol;
output [7:0] Result;
output N,Z,C,V;
wire [7:0] R0,muxout,sum;
wire [7:0] cout;
// Instantiating one 8-bit adder
RippleAdder8b R8b(.sum(sum),.cout(cout),.a(A),.b(muxout),.cin(ALUcontrol[0]));
//2:1 mux to select B or not B
assign muxout = ALUcontrol[0]? ~B : B;
//4:1 mux to select ALU outputs
assign R0= ALUcontrol[0]? A|B : A&B;
assign Result = ALUcontrol[1]? R0 : sum;
// Status outputs
assign N = Result[7];
assign Z = ~|Result;
assign C = ALUcontrol[1] & cout[7];
assign V = ALUcontrol[1] & (cout[7]^ cout[6]);
endmodule
module RippleAdder8b(sum,cout,a,b,cin);
input [7:0] a,b;
input cin;
output [7:0] sum;
output [7:0] cout;
// Instantiating 81-bit full adders
full_adder FA0(.sum(sum[0]),.cout(cout[0]),.a(a[0]),.b(b[0]),.cin(cin));
full_adder FA1(.sum(sum[1]),.cout(cout[1]),.a(a[1]),.b(b[1]),.cin(cout[0]));
full_adder FA2(.sum(sum[2]),.cout(cout[2]),.a(a[2]),.b(b[2]),.cin(cout[1]));
full_adder FA3(.sum(sum[3]),.cout(cout[3]),.a(a[3]),.b(b[3]),.cin(cout[2]));
full_adder FA4(.sum(sum[4]),.cout(cout[4]),.a(a[4]),.b(b[4]),.cin(cout[3]));
full_adder FA5(.sum(sum[5]),.cout(cout[5]),.a(a[5]),.b(b[5]),.cin(cout[4]));
full_adder FA6(.sum(sum[6]),.cout(cout[6]),.a(a[6]),.b(b[6]),.cin(cout[5]));
full_adder FA7(.sum(sum[7]),.cout(cout[7]),.a(a[7]),.b(b[7]),.cin(cout[6]));
endmodule
module full_adder (sum, cout, a, b, cin);
input a, b, cin;
output sum, cout;
wire w1, w2, w3;
// Instantiating 21-bit half adders to make 11-bit full adder
half_adder ha1(w1, w2, a, b);
half_adder ha2(sum, w3, w1, cin);
assign cout = w2|| w3;
endmodule
module half_adder(s, c, a, b);
output s, c;
input a, b;
// sum is a XOR b and carry is a AND b
assign s = a ^ b;
assign c = a & b;
endmodule
Dmem_expected.tv
0000_0001
0000_0001
0000_0010
0000_0011
0000_0101
memories.sv
//64 x 8-bit memory module with one read and one write port
module dmem(clk, we, addr, wr_data, rd_data);
input clk;
input we; // writeenable
input [5:0] addr; // address
input [7:0] wr_data; // write port
output [7:0] rd_data; // read port
reg [7:0] RAM[63:0]; // Memory Array
assign rd_data = RAM[addr]; // Read from address addr
always @(posedge clk) begin
if (we)
RAM[addr]<= wr_data; // Write to address addr the value
end // on the write data port when we =1
// Initialize the memory module
initial begin
RAM[0]=8'h01;
RAM[1]=8'h01;
end
endmodule
module imem(addr,rd_data);
input [3:0] addr; // address
output [11:0] rd_data; // read port
reg [11:0] RAM[12:0]; // Memory Array
assign rd_data = RAM[addr]; // Read from address addr
// Initialize the memory module
initial begin
RAM[0]=12'b000_000_000000; // LD R[0], DMem[0]
RAM[1]=12'b000_001_000001; // LD R[1], DMem[1]
RAM[2]=12'b010_010_000001; // ADD R[2], R[0], R[1]
RAM[3]=12'b010_011_001010; // ADD R[3], R[1], R[2]
RAM[4]=12'b010_100_010011; // ADD R[4], R[2], R[3]
RAM[5]=12'b001_000010_010; // ST R[2], DMem[2]
RAM[6]=12'b001_000011_011; // ST R[3], DMem[3]
RAM[7]=12'b001_000100_100; // ST R[4], DMem[4]
RAM[8]=12'b000_000_000000; // LD [R0], DMem[0]

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