I am having trouble Pipelining my verilog code for a 6 input high/low sorting machine. I need it to output correct answers in 5 clock cycles. Please Help!!

included is my sortTwo module, sort6 and my Dflipflop. My professor hinted at using a 6 bit Dff array after each section of sorting. I am completely lost...

module sortTwo ( output logic [16-1:0] Z[1:0] , input logic [16-1:0] A[1:0] );

assign Z[1] = (A[0] > A[1]) ? A[0] : A[1]; assign Z[0] = (A[0] > A[1]) ? A[1] : A[0];

endmodule // sortTwo

/* * Sort the array * Largest number should be sorted into Z[5], and smallest into Z[0] */

module sort6 ( output logic [15:0] Z[5:0], input logic [15:0] A[5:0] );

logic [15:0] J[5:0]; sortTwo my_0_sort ( J[1:0], A[1:0] ); sortTwo my_1_sort ( J[3:2], A[3:2] ); sortTwo my_2_sort ( J[5:4], A[5:4] );

logic [15:0] K[5:0]; sortTwo my_3_sort ( K[2:1], J[2:1] ); sortTwo my_4_sort ( K[4:3], J[4:3] ); sortTwo my_H_sort ('{K[5],K[0]}, {J[5],J[0]} );

logic [15:0] L[5:0]; sortTwo my_5_sort ( L[1:0], K[1:0] ); sortTwo my_6_sort ( L[3:2], K[3:2] ); sortTwo my_7_sort ( L[5:4], K[5:4] );

logic [15:0] M[5:0]; sortTwo my_8_sort ( M[2:1], L[2:1] ); sortTwo my_9_sort ( M[4:3], L[4:3] ); sortTwo my_I_sort ('{M[5],M[0]}, {L[5],L[0]} );

logic [15:0] N[5:0]; sortTwo my_A_sort ( N[1:0], M[1:0] ); sortTwo my_B_sort ( N[3:2], M[3:2] ); sortTwo my_C_sort ( N[5:4], M[5:4] );

sortTwo my_D_sort ( Z[2:1], N[2:1] ); sortTwo my_E_sort ( Z[4:3], N[4:3] ); sortTwo my_F_sort ('{Z[5],Z[0]}, {N[5],N[0]} );

endmodule // end sort6

module dff #(parameter int size = 1 ) // Our first module parameter! Now everything is squishy ( input logic [size-1:0] d, input logic clk, input logic rst, input logic en, output logic [size-1:0] q );

logic [511:0] rst_val ; // To avoid assigning a constant of unspec length assign rst_val = 512'd0 ;

always_ff @ (posedge clk) begin priority case ( 1'b1 ) (~rst): q[size-1:0] <= rst_val[size-1:0] ; //Reset is active low ( en): q[size-1:0] <= d[size-1:0] ; //Enable is active high default: q[size-1:0] <= q[size-1:0] ; //Default case endcase end

endmodule //dff