I am having trouble with this problem. I would like to know the result and how it can be achieved.

Problem 3: Assume the IF, ID, EX, MEM, and WB stages of a datapath have the following latencies: 380 ps, 140 ps, 320 ps, 580 ps, and 100 ps respectively. What is the clock cycle time in a pipelined and non-pipelined processor? What is the total latency of a load instruction in a pipelined and non-pipelined processor? Assuming that it is possible to split any of the stages in the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you pick to split and what would the new clock cycle time of the pipelined processor be