I have this task to do, but I don't know how to do it. I had two more part before this to do, and I did them but I don't know this one.

Consider the design of a sequential circuit that could control a vending machine. Suppose that a coin-operated vending machine dispenses accepts nickels and dimes. All electronic signals in the vending machine are synchronized to the positive edge of a clock signal, named Clock. The vending machines coin-receptor mechanism generates two signals, senseD and senseN, which are asserted when a dime or a nickel is detected. Because the coin receptor is a mechanical device and thus very slow compared to an electronic circuit, inserting a coin causes senseD or senseN to be set to 1 for a large number of clock cycles. We will assume that the coin receptor also generates two other signals, named D and N. The D signal is set to 1 for one clock cycle after sense D becomes 1, and N is set to 1 for one clock cycle after sense N becomes 1. The timing relationships between Clock, senseD and senseN, D, and N are illustrated in timing diagram bellow. The hash marks on the waveforms indicate that sense D or sense N may be 1 for many clock cycles. Also, there may be an arbitrarily long time between the insertion of two consecutive coins. Note that since the coin receptor can accept only one coin at a time, it is not possible to have both D and N set to 1 at once. (Figure 2 shows circuit that generates N, and Figure 3 provides state diagram for described operation. Write VHDL code for the FSM shown in Figure 3, using the style of code implemented in Lab set 4 part 2. )