I need a cache emulator and I am relying on my experts to put together a solution
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I need a cache emulator and I am relying on my experts to put together a solution in Verilog. Much like assignments you will have in your career, the input and outputs are known but the challenge is figuring out how to get there. The cache emulator should look like the 8-block cache described in chapter 5 of your book on page 386-389.
The 8-block cache will have:
- Index of 3 bits
- 1 bit Valid indicator
- Tag of 2 bits
- Data size will be a word (4 bytes)
- The cache should be initially zero
The memory should be:
- Word size (4 bytes)
- initialized with values starting at 0 and incrementing by 1 at each address.
- Size should be the number of addressable values by cache
Program Operation:
- Input should be the list of values specified from the book (and copied below).
- Output should be:
- Hit/miss along with the data at the memory location specified that is loaded into the block
- Final output of the entire cache contents.
Related Book For
Computer Networking A Top-Down Approach
ISBN: 978-0136079675
5th edition
Authors: James F. Kurose, Keith W. Ross
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