I need help implementing an $8-$bit Up$/$Down counter system in Verilog. Please provide three files:

counter.v $-$ The main counter module with these specifications: Inputs:

clk $($clock signal$)$

reset $($active high reset$)$

control $($up$/$down control signal$)$ Output:

count$[7$:$0](8-$bit counter value$)$

Requirements:

When reset is $1,$ counter resets to $0$

When control is $1,$ count up

When control is $0,$ count down

Use two always blocks:

First block: posedge clk to latch control signal to ctrl Second block: negedge clk or posedge reset for counting based on ctrl

main.v $-$ Top$-$level module that:

Instantiates the counter module

Connects all necessary ports

stimulus.v $-$ Testbench that:

Generates clock signal

Tests reset functionality

Tests both up and down counting

Verifies counter behavior with different control values

Includes proper simulation time and waveform monitoring

Please provide the complete Verilog code for all three files to create a fully functional and testable Up$/$Down counter system.