i need help with the vhdl code,the state, the state diagram, the VHDL model with comments and the results simulation of an FSM with sequence 0101.

the following can be of assistance with the given task

Create a project of the sequence recognizer according to your variant using three processes to describe the finite state machine in VHDL. Draw a state diagram. Verify the VHDL model by simulating them on all possible modes in Xilinx WebPack. Prove that your circuit recognizes the necessary sequence, and do not recognize any of the rest. Record the waveforms. You can capture a screen of the waveforms and save them as a file for insertion in your report. please ensure to include SCREENSHOTS of the simulation along with the vhdl code,the state, the state diagram, the VHDL model of an FSM with sequence 0101.