I need the code and testbench for the given design with an elaborate explanationof an instruction and its operand. The meaning of the syntax Rxlarr$[RY]$ is that the contents of register $RY$ are

loaded into register RX$.$ The mv $($move$)$ instruction allows data to be copied from one register to another. For

the mvi $($move immediate$)$ instruction the expression RxlarrD indicates that the $16-$bit constant $D$ is loaded into

register $Rx.$

Table $1.$ Instructions performed in the processor.

Each instruction can be encoded and stored in the IR register using the $9-$bit format IIIXXXYYY, where III

represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits

are needed to encode our four instructions, we are using three bits because other instructions will be added to the

processor in later parts of this exercise. Hence $IR$ has to be connected to nine bits of the $16-$bit DIN input, as

indicated in Figure $1.$ For the mvi instruction the YYY field has no meaning, and the immediate data #$D$ has to be

supplied on the $16-$bit DIN input after the mvi instruction word is stored into $IR.$

Some instructions, such as an addition or subtraction, take more than one clock cycle to complete, because

multiple transfers have to be performed across the bus. The finite state machine in the control unit "steps through"

such instructions, asserting the control signals needed in successive clock cycles until the instruction has com$-$

pleted. The processor starts executing the instruction on the DIN input when the Run signal is asserted and the

processor asserts the Done output when the instruction is finished. Table $2$ indicates the control signals that can

be asserted in each time step to implement the instructions in Table $1.$ Note that the only control signal asserted in

time step $0$ is $IR$ in$,$ so this time step is not shown in the table.

Table $2.$ Control signals asserted in each instruction$/$time step.

Perform the following task:

Write RTL code using Verilog HDL and Perform simulation by writing testbench.

$($Use VCS simulator$)$

Apply suitable timing, power and area constraints and perform logic synthesis

targeting SAED$32$nm Technology Library

Perform Timing Analysis using Prime Time Analyzer and Optimize the netlist for

timing.