i$)$ The control logic specified in a Moore machine above, has two inputs $($operation and exec$)$ and

eight outputs $($RdX$,$ RdY$,$ WrX$,$ Ain, Gin, Extern, Gout, and add$\_$sub$).$ Based on the state

definitions given above, complete the following truth table.

State RdX RdY WrX Ain Gin Extern Gout add$\_$sub

IDLE $00000000$

LOAD $00100100$

READ$\_$Y

READ$\_$X

ADD

SUB

MV

WRITE$\_$X

DONE $00000000$

III. LAB PROCEDURE

$($i$)$ The first thing to do with your lab partner is reconcile your pre$-$labs. Compare your state

diagrams and truth tables. If they are somewhat different, discuss with each other what made

the differences and make a decision between the two of you about which state diagram you

will try to implement.

$($ii$)$ Since only one person can really type up a Verilog module, one of you should get started on

coding up the state machine that you have decided to pursue. You are to fill in two always

statements in the given skeleton $($l$2\_$sm$.$v$).$ The first one is about state transitions while the

other is to implement the truth table you completed in your pre$-$lab$\mathrm{.}1$

$($iii$)$In the meantime, the other person can bring up Vivado and start pulling in the other pieces

of the system, which the TA will make available to you. Make all connections that are not

dependent on the state machine being instantiated $($in l$2\_$tb$.$v$).$

$2$

$($iv$)$ Once the state machine is coded, import this into Vivado and finish making the connections.

$($v$)$ The TA will provide a testbench, which will cause the design to be simulated across a

number of cycles and will cause each of the four operations to exercised. After running the

simulation, examine the resulting waveforms to see if you can determine if your design is

functioning properly.

$($vi$)$ Once you have determined that your design appears to be working properly, demonstrate to

the TA$.$

$1$ See pages $34-38$ of the Verilog reference for the syntax of always and case statements,

$2$ See pages $29$ and $30$ for of the Veril