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4. Register Transfer Language (RTL) Description Consider the Multi-cycle organization of the MIPS processor. For each of the MIPS assembly language instruction given below: Specify the micro-operations needed to execute the instruction. Identify the control signals that must be asserted for each micro-operation. Complete a table with the following header for each instruction: Clock cycle RTL (micro-operation) Control signals Use a minimum number of clock cycles. Assume that each instruction has been fetched from program memory and is in the IR. (a) load word (b) store word ** Note: An example is provided below: The RTL description for the MIPS ADD instruction executed on the Multi-cycle implementation of the MIPS processor: Control Signals Clock RTL (micro-operation) Cycle 1 ARF[RS], BI -- RF[R] 2 ALUOut +R[A] +R[B] None ALUSCA-1, ALUSrcB-00, ALUcnti "Add" RegDst-1, MemtoReg=0 3 RF[Rd] - ALUOut 4. Register Transfer Language (RTL) Description Consider the Multi-cycle organization of the MIPS processor. For each of the MIPS assembly language instruction given below: Specify the micro-operations needed to execute the instruction. Identify the control signals that must be asserted for each micro-operation. Complete a table with the following header for each instruction: Clock cycle RTL (micro-operation) Control signals Use a minimum number of clock cycles. Assume that each instruction has been fetched from program memory and is in the IR. (a) load word (b) store word ** Note: An example is provided below: The RTL description for the MIPS ADD instruction executed on the Multi-cycle implementation of the MIPS processor: Control Signals Clock RTL (micro-operation) Cycle 1 ARF[RS], BI -- RF[R] 2 ALUOut +R[A] +R[B] None ALUSCA-1, ALUSrcB-00, ALUcnti "Add" RegDst-1, MemtoReg=0 3 RF[Rd] - ALUOut