I wrote the following VHDL code. When I compile the code it displays the following error. What is the error exactly in the (one :) line. And how I fix it?

25x X 267 268 Lab6Part4.vhd Compilation Report - Lab6Part4 - TO 1 Tibrary ieee; 2 use ieee.std_logic_1164.all; 3 Bentity Lab Part4 is 4 port x: in std_logic_vector(1 downto 0); -input s: in std_logic_vector(1 downto 0); --input f: out std_logic --output 8 9 =; 10 Lend Lab6Part4; 11 Barchitecture behavior of Lab6Part4 is 12 signal a: std_logic; 13 signal b: std_logic; 14 15 component Lab6Part3 Eport 17 S: in std_logic_vector (1 downto 0); --input 18 A: in std_logic; --input 19 B: in std_logic; input 20 C: in std_logic; -input 21 D: in std_logic; --input 22 F: out std_logic --output 23 ; 24 -end component; 25 begin 26 27 A S, F => f, A => a, B => b, c => X(0), D => X(1)); 31 32 end behavior; mn co Find... 00 Find Next D Type ID Message 12021 Found 2 design units, including i entities, in source file lab6part4.vhd 12127 Elaborating entity "Lab6Part4" for the top level hierarchy 12006 Node instance "one" instantiates undefined entity Lab6Parts Ensure that required library paths are specified correctly, define the speci Quartus Prime Analysis & Synthesis was unsuccessful 1 error, i warning 293001 Quartus Prime Full Compilation was unsuccessful 3 errors, 1 warning X ages