Identify the error in the below system verilog code and rectify it

class transaction;

bit $[31$:$0]$ data;

int id;

endclass

function void transaction::display$()$;

$display$("$data $=\%0$d and id $=\%0$d$",$ data, id$)$;

endfunction

task transaction::delay$()$;

#$50$;

$display$("$Time $=\%0\mathrm{.}0$t$,$ delayed data $=\%0$d$",$ $time, data$)$;

endtask

module class$\_$example;

transaction tr;

initial begin

tr$.$data $=100$;

tr$.$id $=1$;

tr$.$display$()$;

tr$.$delay$()$;

end

endmodule