Identify the Error in the system verilig code and Rectify It

class transaction$\_$A;

bit $[31$:$0]$ data;

int id;

transaction$\_$B tr$\_$B $=$ new$()$;

function void display$()$;

$display$("$transaction$\_$A: data $=\%0$d and id $=\%0$d$",$ data, id$)$;

$display$("$transaction$\_$B: addr $=\%0$d$",$ tr$\_$B$.$addr$)$;

endfunction

endclass

class transaction$\_$B;

bit $[31$:$0]$ addr $=200$;

endclass

module class$\_$example;

initial begin

tr$\_$A $=$ new$()$;

tr$\_$A$.$data $=100$;

tr$\_$A$.$id $=1$;

tr$\_$A$.$display$()$;

end

endmodule