If FIFO's inputs arrive at the same time, it will be prioritized. (SWP, POP, PUSH, RESET) is the priority order. In other words, when these four commands or other separate commands come, it will do it sequentially, paying attention to the priority of the operation. For example, if the PUSH and RESET commands are input at the same time, the PUSH operation will be performed first and then the RESET operation will be executed.

Even if the FIFO dimensions are still generic, simulate with FIFO at least 16bit wide and at least 8 words deep. Select radixi HEX from the simulation sequence. For example, as for the SWP function, it should be observed as A4F8 after data swap, which is F8A4. PLEASE EXPLAIN EVERY DETAIL OF THE CODE WITH A COMMENT LINE THANKS

YOU NEED TO OPERATE ON THIS CODE:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fifo_memory is generic( constant derinlik : positive :=4; constant genislik : positive :=4 ); Port( PUSH : in std_logic; POP : in std_logic; INIT : in std_logic; SWP : in std_logic; CLK : in std_logic; FULL : out std_logic; EMPTY : out std_logic; NO_PUSH : out std_logic; NO_POP : out std_logic; D_IN : in std_logic_vector(genislik-1 downto 0 ); D_OUT : out std_logic_vector(genislik-1 downto 0):=(others => 'Z') ); end fifo_memory; architecture Behavioral of fifo_memory is type FMEM is array (0 to derinlik-1) of std_logic_vector(genislik-1 downto 0); shared variable UST : integer range 0 to derinlik-1; begin A1: Process(PUSH,POP,INIT,SWP,CLK) variable BLOK : FMEM; variable sayac : integer range 0 to derinlik-1; begin if rising_edge(CLK) then if (PUSH = '1') and (UST <= derinlik-1) then BLOK(UST) := D_IN; NO_POP <= '0'; UST := UST + 1; if UST = derinlik then FULL <= '1'; end if; elsif (PUSH = '1') and (UST = derinlik) then NO_PUSH <= '1'; elsif (POP = '1') and (UST /= 0) then D_OUT <= BLOK(0); NO_PUSH <= '0'; UST := UST - 1; for sayac in 0 to derinlik-2 loop BLOK(sayac) := BLOK(sayac+1); end loop; elsif (POP='1') and (UST=0) then NO_POP <= '1'; elsif ( SWP = '1') and (UST /=0) then for sayac in 0 to derinlik-1 loop BLOK(sayac) := BLOK(sayac)(genislik/2-1 downto 0) & BLOK(sayac)(genislik-1 downto genislik/2); end loop; elsif (INIT='1') then UST := 0; EMPTY <= '1'; for sayac in 0 to derinlik-1 loop BLOK(sayac) := (others => '0'); end loop; end if; end if; end Process A1; end Behavioral; TEST BENCH library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Numeric_Std.all; entity fifo_memory_tb is generic( constant derinlik : positive :=4; constant genislik : positive :=4 ); end; architecture bench of fifo_memory_tb is component fifo_memory generic( constant derinlik : positive :=4; constant genislik : positive :=4 ); Port( PUSH : in std_logic; POP : in std_logic; INIT : in std_logic; SWP : in std_logic; CLK : in std_logic; FULL : out std_logic; EMPTY : out std_logic; NO_PUSH : out std_logic; NO_POP : out std_logic; D_IN : in std_logic_vector(genislik-1 downto 0 ); D_OUT : out std_logic_vector(genislik-1 downto 0):=(others => 'Z') ); end component; signal PUSH: std_logic; signal POP: std_logic; signal INIT: std_logic; signal SWP: std_logic; signal CLK: std_logic; signal FULL: std_logic; signal EMPTY: std_logic; signal NO_PUSH: std_logic; signal NO_POP: std_logic; signal D_IN: std_logic_vector(genislik-1 downto 0 ); signal D_OUT: std_logic_vector(genislik-1 downto 0):=(others => 'Z') ; constant clock_period: time := 10 ns; signal stop_the_clock: boolean; begin -- Insert values for generic parameters !! uut: fifo_memory generic map( derinlik => 4 , genislik => 4 ) port map ( PUSH => PUSH, POP => POP, INIT => INIT, SWP => SWP, CLK => CLK, FULL => FULL, EMPTY => EMPTY, NO_PUSH => NO_PUSH, NO_POP => NO_POP, D_IN => D_IN, D_OUT => D_OUT ); stimulus: process begin -- Put initialisation code here PUSH <= '0'; POP <= '0'; INIT <= '1'; SWP <= '0'; D_IN <= "0000"; WAIT FOR 10 NS;

PUSH <= '1'; POP <= '0'; INIT <= '0'; SWP <= '0'; D_IN <= "0001"; WAIT FOR 10 NS; PUSH <= '1'; POP <= '0'; INIT <= '0'; SWP <= '0'; D_IN <= "0001"; WAIT FOR 10 NS; PUSH <= '1'; POP <= '0'; INIT <= '0'; SWP <= '0'; D_IN <= "0010"; WAIT FOR 10 NS; PUSH <= '1'; POP <= '0'; INIT <= '0'; SWP <= '0'; D_IN <= "1000"; WAIT FOR 10 NS; PUSH <= '0'; POP <= '0'; INIT <= '0'; SWP <= '1'; D_IN <= "0000"; WAIT FOR 10 NS; PUSH <= '0'; POP <= '1'; INIT <= '0'; SWP <= '0'; D_IN <= "0000"; WAIT FOR 10 NS; PUSH <= '0'; POP <= '1'; INIT <= '0'; SWP <= '0'; D_IN <= "0000"; WAIT FOR 10 NS; PUSH <= '0'; POP <= '1'; INIT <= '0'; SWP <= '0'; D_IN <= "0000"; WAIT FOR 10 NS; PUSH <= '0'; POP <= '1'; INIT <= '0'; SWP <= '0'; D_IN <= "0000"; WAIT FOR 10 NS; -- Put test bench stimulus code here

stop_the_clock <= true; wait; end process; clocking: process begin while not stop_the_clock loop CLK <= '0', '1' after clock_period / 2; wait for clock_period; end loop; wait;