If two identical processors are used to execute different threads of the same process, it is called:

a.) Multi-processing

b.) Multi-programming

c.) SMP

d.) Multi-core

If a DMA needs to transfer 16MB/s, and the data can be transfered in independent packets of the same size. The designer can choose the packet size between 2KB, 4KB, and 8KB. Which size would allow the DMA to steal the least number of cycles from the processor per second?

a.) 2KB

b.) 4KB

c.) 8KB

d.) The size of the packets doesnt affect the total # of cycles per second the DMA steals from the processor.

MESI protocol is implemented in:

a.) Cache tag

b.) Cache index

c.) Cache block

d.) None of the above

Cache coherency in general is less in this type of scheme:

a.) Write through

b.) Write back

c.) Write buffer

d.) All of the above

Shared L2 Caches is common in:

a.) Uniprocessor

b.) Workstation SMP

c.) General SMP

d.) None of the Above