Question: Implement a 16-bit version of the ALU using Verilog HDL and analyze by simulating it. The ALU operation that should be included ADD, SUB, AND,
Implement a 16-bit version of the ALU using Verilog HDL and analyze by simulating it. The ALU operation that should be included ADD, SUB, AND, OR and SLT. A Zero output is not required. - Circuit diagrams of the ALU down to the gate level.
- Critical Path & Delay of the ALU under unit gate delay model
- gate cost of the ALU
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