Implement Boolean function Y$=($A$.$B$+$C$)$ using unfooted dynamic logic such that

each logic gate has a maximum valency of two inputs $($not including the clock$)$

and the output of each gate is guaranteed to be monotonically rising with the help

static CMOS inverters.

$(1)$ Draw the gate$-$level and transistor$-$level schematic of this circuit. Size the

transistors in the transistor$-$level schematic to have unit pull$-$down

resistance and double pull$-$up resistance in the dynamic gates and unit

pull$-$down and pull$-$up resistance in the CMOS gates $($assume n $=2$ p$).$

$(15$ points$)$

$(2)$ Calculate the logical effort gA at input A$.$ How does it compare with the

logical effort at input A of the static CMOS design using gates with a

maximum valency of two $($show the gate$-$level schematic of your static

CMOS design to avoid ambiguity$)?(10$ points