Implement the inverter shown in Fig $1$ using $18-$nm FinFET GPDK

$($a$)$ using Cadence Simulate the inverter using transient analysis for a load capacitance of CL $=5$ fF$.$ Present waveforms at the input $($A$),$ and at the output $($F$).$ Select the size of the transistors so that tpHL $=$ tpLH$.$ Extract the values of the propagation delays from the waveforms.

$($b$)$ using Cadence Implement the circuit in Fig $2$ and size the transistors in a way that the longest propagation delays for the low$-$to$-$high and the high$-$to$-$low transitions match with that of the inverter. $($i$)$ Present the output waveform when A $=$ B $=$ C $=0,$ D $=1$ and A $=0,$ B $=$ C $=1,$ D $=0$ and extract the corresponding propagation delays.