In a computer with a conveyor architecture and instruction length between 1 and 5 bytes, the code of the operation consists of 5 bits. It is decoded by a decoder and fed to an arithmetic-logic device for execution. The decoder is O a. 1 of 5 demultiplexer b. 3:5 decoder O c. 5:32 decoder Od 32:5 decoder O e multiplexer 5 to 1 Of. 5:3 decoder O g. a sequential logic circuit 0 h. a 5-bit shift register