In a paging system, the process space is divided into consecutive pages of fixed length: Page 0, Page 1, Page 2, etc.

As such, a logical address (also called a virtual address) consists of:

Page #

Offset

In a paging system, main memory is divided into consecutive frames of fixed length (same length as the pages):

Frame 0, Frame 1, Frame 2, etc.

Some of the logical pages are placed in the physical frames. For example, pages 3, 8 and 10 might be placed in frames 104, 87 and 378, respectively, with the other pages of the process in virtual memory, i.e., on disk (or other form of secondary memory). The goal of this exercise is to help you understand the Simple indexing and Multi-level indexing for converting a logical address (page number + offset) to a physical address (frame number + offset, or a page fault if the page is not in main memory):

Throughout this exercise, logical addresses and physical addresses are written as pairs of numbers (page number offset for logical addresses, frame number/offset for physical addresses).

Diagram:

Main Memory

Address Present Bit | Frame Number

0 104

1 334

2 45

3 891

4 115

256 0 333

257 0 228

258 0 610

259 0 200

260 1 324

261 1 900

262 1 1005

263 0 820

264 1 20

265 0 5

266 0 1005

267 0 220

268 1 4

269 1 303

270 1 689

271 0 446

272 1 848

273 0 666

274 1 111

275 1 229

Answer the following questions based on the above (completed) diagram.

Consider a 32-bit addressing scheme with 18 bits for the page number and 14 for the offset. How many entries in the page table? What is the size of each page?