Question: In a pipelined processor, assume that there are no pipeline stalls. The breakdown of executed instructions is as follows: sub add addi not beq lw

In a pipelined processor, assume that there are no pipeline stalls. The breakdown of executed instructions is as follows:
sub add addi not beq lw sw
5%10%5%5%30%30%15%
a.[5 points] In what percentage of all cycles is the data memory used?
b.[5 points] In what percentage of all cycles is the input of the sign-extend circuit needed?

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