In a system with 2-level paging, each virtual adderss (p1, p2, d) requires three memory references. To speed up the address translation, a TLB holds the components (p1, p2) together with the corresponding frame number. If each memory access takes m ns and the access to the TLB takes m/10 ns, determine the hit ratio (the percentage of references where the entry is found in the TLB) necessary to reduce the average access time to memory by 50%.

In a system with 2-level paging, each virtual adderss (p1, p2, d) requires three memory references. To speed up the address translation, a TLB holds the components (p1,p2) together with the corresponding frame number. If each memory access takes m ns and the access to the TLB takes m/10ns, determine the hit ratio (the percentage of references where the entry is found in the TLB) necessary to reduce the average access time to memory by 50%