(in computer Organization and design(Datapath))

The single-cycle MIPS processor below has been annotated with delays for several of the modules (e.g., the register file has a 40ps delay). Assuming the unlabeled modules have (5 delay), give the critical path delay for the following instructions: i- R-Type instruction ii- Load instruction iii- Store instruction iv- Beq instruction v- Jump

Given these critical paths, what is the maximum frequency for this datapath? Single cycle MIPS Processor