(in computer Organization and design(Datapath))

The single-cycle MIPS processor below has been annotated with delays for several of the modules (e.g.,R-type = instruction memory 200 + register file 40 +alu 70 +write 40 (in the zero delay)). Assuming the unlabeled modules have (10 delay), give the critical path delay for the following instructions: i- R-Type instruction ii- Load instruction iii- Store instruction iv- Beq instruction v- Jump

Given these critical paths, what is the maximum frequency for this datapath? Single cycle MIPS Processor