In general, a processor performs a read from memory or a read from an I$/$O device, by

sending a read request along with the read address during one clock cycle and obtains the

requested data as early as in the next clock cycle depending on the speed of the memory or I$/$O

device. If the requested data can$$t be returned within the next clock cycle, the processor must

pause and wait one or more extra additional cycles for the data to become available. These extra

clock cycles are referred to as $$wait states$.$ Zero wait states are required if the requested data is

available in the next clock cycle.

a$)(3)$ Suppose device $1$ requires no wait states. What is the maximum number of reads per

second that a processor can perform running at a $100$ MHz clock rate?

b$)(3)$ Due to the number of wait states required for device$2,$ the processor can perform at most $4$

million reads per second running at a $80$ MHz clock rate. How many wait states does device$2$

require for each read?

c$)(3)$ Due to the number of wait states required for device$3,$ the processor can perform at most

$11$ million reads per second running at a $44$ MHz clock rate. How many wait states does device$3$

require for each read?