In lecture 1, we covered D flip-flop as an example for sequential logic circuits. Use the code from the\ lecture as a start and implement the following two versions of the D flip-flop:\ D flip-flop with synchronous set/reset. (filename: dff SR.v)\ D flip-flop with asynchronous preset/clear. (filename: dff PC.v)\ Design two testbenches to test for the correct operation of the two version of D flip-flop. Show the\ waveform from your testbench. Explain on your waveform how your flip-flop works correctly as expected.\ File names should be (filename: tb dff SR.v), and(filename: tb dff PC.v).\ The module declarations in your code for this question must be as follows:\ D flip-flop with synchronous set/reset: module dff SR (clk, d, set, reset, q);\ D flip-flop with asynchronous preset/clear: module dff PC (clk, d, preset, clear, q);\ Note: If the simulation of the new testbenches does not show up, you should do the following:\ File > Close Simulation\ Right-Click on the testbench you want to simulate > Set as Top\ Run the simulation again.