in the 32 bit processor given, what would the control values have to be in verilog to implement logical left, logical right, and arithmetic shift right

3 MIPS processor After you modify the code, your processor would have the following control path and datapath. Jump address Instruction (25-0) Shift left 2 26 28 Add X3 >Add roSUR ALU 0 Shift left 2 RegDst Jump Branch MemRead Instruction (31-26] MemtoReg Control ALUO MemWrite ALUSC RegWrite Instruction (25-21) PC - Read address Read Instruction (20-16) Read register 1 Read data 1 register 2 Write Read Zero ALU ALU Instruction (31-0) Instruction memory 0 M Instruction [15-11 result Address Read data register data 2 u u Write data Registers Write Data data memory Instruction (15-0) 16 32 Sign- extend ALU control Instruction (5-0) Figure 2: modified mips processor. Use Table 4 to modify control, ALUControl, and ALU files. 6'b110000: begin // sil, Srl, sra reg_dst = 1'bo; mem_to_reg = 1'bo; alu_op = 2'610; mem_read = 1'b0; mem_write = 1'bo; alu_src = 1'bo; reg_write = 1'bo; jump = 1'bol branch = 1'b0; 3 MIPS processor After you modify the code, your processor would have the following control path and datapath. Jump address Instruction (25-0) Shift left 2 26 28 Add X3 >Add roSUR ALU 0 Shift left 2 RegDst Jump Branch MemRead Instruction (31-26] MemtoReg Control ALUO MemWrite ALUSC RegWrite Instruction (25-21) PC - Read address Read Instruction (20-16) Read register 1 Read data 1 register 2 Write Read Zero ALU ALU Instruction (31-0) Instruction memory 0 M Instruction [15-11 result Address Read data register data 2 u u Write data Registers Write Data data memory Instruction (15-0) 16 32 Sign- extend ALU control Instruction (5-0) Figure 2: modified mips processor. Use Table 4 to modify control, ALUControl, and ALU files. 6'b110000: begin // sil, Srl, sra reg_dst = 1'bo; mem_to_reg = 1'bo; alu_op = 2'610; mem_read = 1'b0; mem_write = 1'bo; alu_src = 1'bo; reg_write = 1'bo; jump = 1'bol branch = 1'b0