In the circuit diagram above, Computing Logic $1$~$4$ are simple combinational circuits, and Register$1$ and Register$2$ are both positive$-$edge$-$triggered DFFs$.$ The delays of Computing Logic $1$~$4$ are known to be $3$ns$,2$ns$,2$ns$,$ and $6$ns respectively. $($Assume there are no other delays.$)$

$($a$)$ If a pipeline register is to be added at one of the points A$,$ B$,$ or C$,$ which point is the better choice? Please explain the reason $(2\%).$

$($b$)$ Considering only the delays of Computing Logic $1$~$4$ and no other delays, if pipeline registers are added at points A and C$,$ what is the minimum clock cycle time that can be set without causing a timing violation? Please explain the reason $(2\%).$

$($c$)$ Assuming the computation loads of Computing Logic $1$~$4$ are $45,40,50,$ and $60$ operations respectively, calculate the throughput for the setup described in part $($b$)(2\%).$

$($d$)$ Based on the structures described in parts $($a$)$ and $($b$),$ which configuration $($adding one or two pipeline registers$)$ would result in higher throughput? Please explain the reason $(2\%).$Pipeline $(8\%$