In the following indicate all Read Before Write hazards. Circle the offending registers and connect them with a line. Assume hazards exist indefinitely $($unlike in the pipeline model where data hazards resolve by stalling $2$ clock cycles$)$

add $$3,$ $$4,$ $$5$

add $$4,$ $$3,$ $$5$

add $$4,$ $$5,$ $$5$

add $$3,$ $$3,$ $$6$

add $$7,$ $$8,$ $$3$