Question: In the following processor design, when executing the instruction beq $s 1 , $t 1 , offset, please answer: 1 ) what would be the

In the following processor design, when executing the instruction beq $s1, $t1, offset, please answer: 1) what would be the output of the logic block highlighted in red 2_ what would be the next PC value? 3) what type of addressing method is used?

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