Question: In the following VHDL process A , B , C , and D are all integer signals. A , B , and C initially have

In the following VHDL process A, B, C, and D are all integer signals. A,B, and C
initially have a value of 5 at time 15ns, and D initially has a value of 10. If E changes
from 0 to 1 at time 20ns, specify the time(s) at which each signal will change and the
value to which it will change. List all changes to Time values, Queue values and
Current values in chronological order (1,1+delta, 1+2delta, 3 etc.), and complete the
table below. You may not need to use all scheduling slots.
Q5: process (E)
begin
A <=1 after 5ns;
B <= A +10;
C <= B +1 after 4ns;
D <= A after 7ns;
B <=16 after 10ns;
end process Q5;

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