In the table on the side, the data written in the memory cells of a ROM circuit can be seen. Write the VHDL topic of the ROM circuit in question with the dataflow architecture, with the address indicated by the vector A=A2A1A0 and the data as the vector D=D4D3D2D1D0.

Note: please answer on a piece of paper.

\begin{tabular}{|c|c|} \hline A2A1A0 & D4D3D2D1D0 \\ \hline 000 & 11010 \\ \hline 001 & 10111 \\ \hline 010 & 01101 \\ \hline 011 & 11101 \\ \hline 100 & 00011 \\ \hline 101 & 01001 \\ \hline 110 & 00010 \\ \hline 111 & 01110 \\ \hline \end{tabular}