In this architecture the logic and arithmetic instructions, except for mul and div are executed in stage X$2.$ The instructions for mul and div require $3$ and $4$ cycles respectively and hence produce their result in the end of stage X$3$ and X$4$ respectively. The instructions of memory access require $2$ cycles $($stages X$2,$ X$3),$ while the address calculation occurs at stage X$2.$ The resolution of conditional branches takes place at X$2$ and in case that the branch gets executed, the pipeline is flushed and from the next cycle the correct instruction is fetched. Last, the write to a register occurs at the $1"$ half of a cycle while the read from the same register occurs at the $2$nd half of the same cycle. We are asked to execute the following piece of code:

$2$