In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: [17pts] 3. IF ID EEX MEM | WB 250ps 350ps 150ps300ps200ps a. what is the clock cycle time in a pipelined and non-pipelined (ie, single cycle) processor? what is the total latency of one lw instruction in a pipelined and non-pipelined (i.e., single cycle) processor? b. What is the total latency of executing 1000 1w instructions in a pipelined and non-pipelined processor (assume there are no data dependencies between the instructions)? What is the speedup achieved by using pipelining in this example? c. d. If you could split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split, and what is the new clock cycle time of the processor