In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: ID EX MEM WB L 400ps 300ps 200ps | 350ps 250ps E D EX MEM WB Also, assume that instructions executed by the processor are distributed as follows: ALU BEQ LW SW 40% 30% 20% 10% a. What is the clock cycle time in a pipelined and non-pipelined processor? b. What is the total latency of an LW instruction in a pipelined and non-pipelined processor? c. If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what are the new clock cycle time and latency of an LW in the pipelined processor? d. Assuming there are no stalls or hazards, what is the utilization of the data memory? e. Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? f. Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another is fetched. In this organization, an instruction only goes through stages it actually needs (e.g., SW only takes 4 cycles because it does not need the WB stage). What are the average cycle times of each type of processors (single-cycle, multi-cycle, and pipelined)