In this project, you will design a simple Arithmetic Logic Unit $($ALU$)$ using Verilog

Hardware Description Language $($HDL$).$ The ALU should be capable of performing four

basic arithmetic and logic operations: addition, subtraction, bitwise AND, and bitwise

OR$.$

Objective:

$$ To develop a comprehensive understanding of Verilog HDL for hardware

description.

$$ To design and implement a simple ALU with four basic functionalities.

$$ To explore structural, dataflow, and behavioral modeling techniques in Verilog.

Tasks:

$1.$ ALU Design:

o Define inputs and outputs of the ALU