In this project, you will write a cache simulator which takes an image of memory and a memory trace as input,simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses, and evictions for each cache type along with the content of each cache at the end.

Your simulator will take the following command-line arguments:

Usage: ./your_simulator -L1s -L1E -L1b

-L2s -L2E -L2b

-t

-L1s: Number of set index bits for L1 data/instruction cache (S = 2s is the number ofsets)

-L1E: Associativity for L1 data/instruction cache (number of lines per set)

-L1b : Number of block bits for L1 data/instruction cache (B = 2b is the blocksize)

-L2s: Number of set index bits for L2 cache (S = 2s is the number ofsets)

-L2E: Associativity for L2 cache (number of lines per set)

-L2b : Number of block bits for L2 cache (B = 2b is the blocksize)

-t : Name of the trace file (see Reference TraceFiles part below)

The command-line arguments are based on the notation (s, E, and b) from page 652 of the CS:APP3e textbook. The s, E, and b values will be the same for both L1 data and instruction caches.

For example, if you want to simulate a fully associative (s=0) L1 cache of 2 lines (E=2) and 8 blocks (b=3), and a 2-way set associative (E=2) L2 cache of 2 sets (s=1) and 8 blocks (b=3), and see the results for the trace file test1.trace,you will run your program with the arguments given in the following example. Also, the results should be in the given format.

linux> ./your_simulator -L1s 0 -L1E 2 -L1b 3 -L2s 1 -L2E 2 -L2b 3 -t test1.trace

L1I-hits:0 L1I-misses:1 L1I-evictions:0

L1D-hits:1 L1D-misses:1 L1D-evictions:0

L2-hits:1 L2-misses:2 L2-evictions:0

L 5, 3

L1D miss, L2 miss

Place in L2 set 0, L1D

I 10, 8

L1I miss, L2 miss

Place in L2 set 0, L1I

S 0, 1, ab

L1D hit, L2 hit

Store in L1D, L2, RAM

Programming Rules

Your simulator must work correctly for different sets of s, E, and b values for each cache type. This means that you will need to allocate storage for your simulators data structures using the malloc function. Type man malloc for information about this function.

For this project, we are interested in L1 data cache, L1 instruction cache, and unified L2 cache performance.

Each of the caches will implement write-through and no write allocate mechanism for store and modify instructions.

For the evictions, FIFO (first in first out)policy will be used.

For each cache (L1D, L1I, L2), you must print the total number of hits, misses, and evictions, at the end of your program.

You should assume that memory accesses are aligned properly, such that a single memory access never crosses block boundaries (Read and write requests are less than or equal to block size).