In this question, we will explore the different types of cache misses, and see how they affect memory latency. Consider the MIPS assembly code shown below, which contains the address and content of each instruction. The instruction cache is Direct Mapped with eight 16-Byte cache lines.

Address	Instruction	Iteration 1	Iteration
	loop:
0x108	addiu r1, r1, -1
0x11c	addiu r2, r2, 1
0x110	j foo
	...
	foo:
0x218	addiu r6, r6, 1
0x21c	ben r1,r0, loop

The register R1 is initially set to 32, which means there will be 32 iterations of this loop.

Question 2.A Catagorizing Cache Misses Assume that the cache is initially empty. For the first two iterations of the loop, fill the appropriate column (iteration 1 and iteration 2), with the appropriate type of miss that will occur (compulsory, conflict, capacity), or leave it blank if you think there is a cache hit. Rank the type of misses based on their frequency(most common to least common) for the above code.

Question 2.B Latency Based on the code shown above, calculate the instruction cache miss rate for 32 iterations of the loop. Also calculate the average instruction cache access latency for 32 iterations of the loop, in terms of cycles, given that the hit time is 1 cycle and miss penalty is 6 cycles. Show your work, as this calculation has more than one step.