In verilog, please implement a Serial$-$Input$-$ParallelOutput $($SIPO$)8-$bit register. A PISO is a hardware structure that loads parallel data $($multiple bits$)$ on the input side and serializes it $($one bit at a time$)$ on the output side. A SIPO is a hardware structure that is the opposite of a PISO. Both structures are modifications of a basic shift register with additional hardware to account for these functionalities. Use any level of modeling

Design an $8-$bit SIPO register with input serial$\_$in $(1$ bit$)$ and output parallel$\_$out$[7$:$0](8$ bits$)$ that will parallelize the input in $8$ clock cycles. The first output bit is parallel$\_$out$[0]($LSB$-$first$)$ and then $1$ bit per cycle until parallel$\_$out$[7]($MSB$).$ The core of the shift register will be composed of the basic DFF described in class $($input d$,$ output q$,$ input clk$)$ and modified as needed to add the capability for an active$-$high synchronous reset $($input rst$).$ Additional gates may be needed in order to add the ability for the SIPO module to shift data $($active$-$High input shift$)$ into the appropriate location in the output register.

I need the drawn pen$-$and$-$paper$/$digital diagram for the SIPO unit, needed modules, and testbench for testing purposes that show clear timing diagram screenshots with $8$ bits on input being parallelized through your SIPO module.