In verilog....please implement this code below to gate level.

module mux_2x1 (A,B,Select,Out);

input A,B,Select;

output Out;

not n1 (notSel,Select);

and a1 (O1,A,notSel),

a2 (O2,B,Select);

or or1 (Out,O1,O2);

endmodule

module mux_4x1 (A,B,C,D,S,Out);

input A,B,C,D;

input [1:0] S;

output Out;

mux_2x1 m0 (A,B,S[0],O1),

m1 (C,D,S[0],O2),

m2 (O1,O2,S[1],Out);

endmodule